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For Home Electronics and Security Devices Camera Image Processor Series
Camera Image Processor with ADPCM / MIDI / MP3 / AAC / HE-AAC Audio
BU6569GVW
Description BU6569GVW is a camera image processor with ADPCM/MIDI/MP3/AAC/HE-AAC Audio. Features 1) Built-in Camera Module Interface UXGA size (16001200) for input of image data up to 7.5 fps, SXGA size (12801024) for input of image data up to 15fps and VGA size (640480) for input of image data up to 30fps (zooming function available). Input data format for YUV=4:2:2, RGB=4:4:4 (8 bits for each RGB). Filter processing (image processing) to input images (2 gradations / gray scale / sepia / emboss / edge enhancement / negative). Multi-step size reduction down to 1/16 in X- and Y-direction possible, cutting out into an arbitrary size after resizing. Cut images to be stored into an arbitrary position in frame memory in YUV=4:2:2 format or RGB=5:6:5 format (16bit/pixel). 2) Built-in frame memory / JPEG code memory Built in image frame memory (160KB to store 1 frame of 320240@16bit/pixel). Data to be stored into image frame memory in YUV=4:2:2 format or RGB5:6:5 format (16bit/pixel). An arbitrary position of frame memory to be updated to camera image according to mask frame memory. Mask data to be stored into mask frame memory in 1bit/2pixels in YUV=4:2:2 format or 1bit/1pixels in RGB=5:6:5 format. Rectangular writing function and rectangular reading function as transparent color to image frame memory. Frame memory is usable as JPEG code memory (192KB) to store JPEG compressed images. Frame memory is usable as a ring buffer for JPEG code of 192KB or more. 3) Built-in LCD controller interface Built-in input/output interface which type is CPU I/F, to LCD controller For display colors of 262144 colors / 65536 colors / 4096 colors. Up to 2 LCD module controllers, MAIN and SUB, controllable. Arbitrary rectangular selection in frame memory to be transferred to LCD controller. Multi-step scaling process in the range of 1/4 to 2 in X- and Y-direction is available to display images from frame memory to the LCD. 4) Extended overlay function Supporting overlay of icon-data up to two icons with LCD data transfer. Icon-data corresponding to 65536 display colors. Possible to setting transparent colors. 5) Built-in TV encoder interface Connection to ROHM-made BU9972GU or BU9969KN. Optional rectangular area of frame memory transferable to TV encoder IC. Multi-step scaling process in the range of 1 to 8 in X- and Y-direction is available for display images from frame memory to the TV encoder IC.
No.09061EAT04
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6) Built-in JPEG CODEC ISO/IEC10918 conforming base line method. Compression For YUV=4:2:2 format only. Quantization table selectable from 32 built-in tables. Decompression
Technical Note
For YUV=4:4:4, 4:2:2(horizontal sub-sampling), 4:2:0, 4:1:1(horizontal sub-sampling), and gray scale. 7) Built-in HOST CPU interface Adaptable to 16bit bus interface. Read/Write access to/from frame memory. Read/Write access to/from internal registers (Indirect access with a index register as the address). Read/Write access to/from the LCD controller: Parallel/Serial (Direct access available via the LCD interface). 8) Built-in USB interface USB 2.0 FS adaptable to mass storage class. 9) Built-in NAND Flash memory interface Adaptable to 8bit and 16bit width for data bus. ECC calculation by BU6569GVW. 10) Built-in SD card interface Built-in host controller block of SD card interface, MMC interface. 11) AAC Decode Supporting Advanced Audio Coding, Low complexity (AAC-LC) Supporting High Efficiency Advanced Audio Coding (HE-AAC) 12) MP3 Decode ISO/IEC 11172-3 (32, 44.1 or 48 KHz) 13) Melody source Simultaneous generation of up to 64 polyphonic tones out of a tone palette of 128 sounds plus 47 drum set sounds, 15 electric drum set sounds, and 32 effect sounds. Up to 8 user customized sound can be used to create original sounds. Supporting 12-bit pitch bending and modulation support. Plays up to four songs simultaneously and supports real-time modification of tempo, key, volume, and pan pot. 14) ADPCM CODEC Built-in ADPCM decoder/PCM player (2 channels), enables mixing with melody. Built-in ADPCM encoder/PCM recorder (1 channel). 15) IIS, PCM interface Digital input IIS interface (IIS, Standard Left Justified format, and Standard Right Justified format) PCM interface (G711.1 u-Law, G711.1 A-Law, Linear (negative number is expressed as 2's-complement.)) Digital output IIS interface (IIS, Standard Left Justified format) 16) Stereo DAC block Built-in a stereo digital-analog converter. The DAC block's dynamic range is 1.98 Vpp (typ.) LPF is included as a smoothing filter subsequent to DAC output, which can eliminate the high-frequency components of the generated analog waveform. 17) Auto Play AAC/HE-AAC/MP3 music can be played automatically in SD card or Flash memory of 512B/page and 2KB/page by using auto play file list (link information of page address) written into Play List RAM by HOST CPU. 18) Clock generation, power management function Two oscillation circuits configuration by XIN1, 2 and XOUT1, 2 terminals, or clock input available from the XIN1, 2 terminal. Built-in two PLL circuits enable clock multiplication. Clock control of BU6569GVW inside in unit of block (suspend mode available.) Data is prepared separately about each register setup. Please refer to the Development Scheme on page 14.
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Technical Note
System1 (VDDIO1)
P2-P6(D8-D4),P8-P27(D3-D0,ADVB,CSB, WRB,RDB,INT,RESETB,LED0,VIB0,DIGLR, DIGCK,DACMCK,DIGDIN,DIGDOUT,FSYNC, PCMDIN,DCLK) ,P112-P120(A2,A1,D15-D9) P42-P43(SD_CLK,SD_CMD),P45-P61(SD_DAT0,FL_CEB,FL_RB,LCDCS1B, LCDCS2B,LCDWRB,LCDRDB,LCDA0,TEST,LCDD0-LCDD7), P63-P72(LCDD8-LCDD17),P74-P80(CAMRST,SDA,SDC,CAMCKI,CAMCKO,CAMVS,CAMHS), P82-P89(CAMD0-CAMD7),P92-P102(TE_VSYNC, TE_HSYNC,TE_PIXCLK,TED0-TED7) P37-P39(USB_DM,USB_DP,USB_RDY) P105-P109(XIN1,XOUT1,PLL_FILTER,XIN2,XOUT2) P29-P30(L_OUT,R_OUT),P34-P35(VREF,MONO_OUT)
System 2 (VDDIO2)
System 3 (VDDIO3) System 4 (VDDIO4) System 5 (AVDD)
Application Security camera, Intercom with camera, Drive recorder and Web camera etc.
Lineup
Power source voltage
Parameter
IO1:HOSTI/F IO2:Camera, LCD
Camera interface
HOST CPU interface
LCD interface
[Image] Codec [Sound /Music]
Multimedia interface
Package
BU6569GVW
1.7-3.6V(VDDIO1) 2.7-3.6V(VDDIO2) *1 3.0-3.6V(VDDUSB) *2 1.45-1.55V(VDD Core)
Supported up to 2M pixels. (1600x1200)
16bit bus 80 systems CPU Interface
Supported up to QVGA (320x240)
2M pixels JPEG Codec Motion-JPEG 64MIDI/MP3/AAC / HE-AAC decode ADPCM Codec
USB2.0 FS I/F, SDC / MMC I/F, TV encoder I/F, NAND Flash, Memory I/F
SBGA120W080
*1 VDDIO2, VDDIO4, and AVDD can be used by the same source voltage. *2 VDDUSB is the same as VDDIO3.
Absolute maximum ratings
Parameter Applied power source voltage 1 (IO1) Applied power source voltage 2 (IO2) Applied power source voltage 3 (USB) Applied power source voltage 4 (PLL) Applied power source voltage 5 (DAC) Applied power source voltage 6 (CORE) Input voltage Storage temperature range Power dissipation Symbol VDDIO1 VDDIO2 VDDIO3 VDDIO4 AVDD VDD VIN Tstg PD
(Ta=25)
Rating -0.3+4.2 -0.3+4.2 -0.3+4.2 -0.3+4.2 -0.3+4.2 -0.3+2.1 -0.3VDDIO+0.3 -40+150 380 Unit V V V V V V V mW
Recommended operating range
Parameter Applied power source voltage 1 (IO1 Applied power source voltage 2 (IO2 Applied power source voltage 3 (USB) Applied power source voltage 4 (PLL) Applied power source voltage 5 (DAC) Applied power source voltage 6 (CORE) Input voltage range Operating temperature range Symbol VDDIO1 VDDIO2 VDDIO3 VDDIO4 AVDD VDD VIN Topr Rating 1.703.60 (Typ:3.30V) 2.703.60 (Typ: 3.30V) 3.003.60 (Typ:3.30V) 2.703.60 (Typ: 3.30V) 2.703.60 (Typ: 3.30V) 1.451.55 (Typ:1.50V) 0VDDIO -30+85 Unit V V V V V V V
Please supply power source in order of VDDVDDIO. VDDIO1 VDDIO2 VDDIO3 VDDIO4 ADD
Power dissipation is IC only. In the case exceeding 25C, 3.8mW should be reduced at the rating 1C.
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Electric characteristics Unless otherwise specified, VDD=1.50V,VDDIO1,2,3,4,AVDD=3.30V,GND=0V,Ta=25, fXIN1=12.0MHz,fXIN2=12.0MHz,fAUDIO=74.0MHz,fIMAGE=52.0MHz
Parameter Input frequency 1 Input frequency 2 Internal clock frequency 1 Internal clock frequency 2 Operating consumption current 1 Operating consumption current 2 Static consumption current Input "H" current 1 Input "H" current 2 Input "H" current 3 Input "L" current 1 Input "L" current 2 Input "L" current 3 Input "H" voltage1 Input "L" voltage 1 Input "H" voltage 2 Input "L" voltage 2 Hysteresis voltage width Input "H" voltage3 Input "L" voltage 3 Differential input sensitivity Differential common mode range Output "H" voltage 1 Output "L" voltage 1 Output "H" voltage 2 Output "L" voltage 2 Output "H" voltage 3 Output "L" voltage 3 Output "H" voltage 4 Output "L" voltage 4 VREF PIN voltage Analog output voltage range Analog amplitude Output load for analog output Symbol fXIN1 fXIN2 fIMAGE fAUDIO IDD1 IDD2 IDDst IIH1 IIH2 IIH3 IIL1 IIL2 IIL3 VIH1 VIL1 VIH2 VIL2 Vhys VIH3 VIL3 VDI VCM VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 VOH4 VOL4 VVREF VAOUT VAMP RAOUT MIN. 2.688 10.0 -10 25 -10 -10 -10 -160 VDDIO*0.8 -0.3 VDDIO*0.85 -0.3 2.0 0.2 0.8 VDDIO-0.4 0.0 VDDIO-0.4 0.0 VDDIO-0.4 0.0 2.8 0.0 0.475*AVDD 0.47*AVDD 10 Limits TYP. 12.8 17.3 50 -80 0.9 0.5*AVDD 0.5*AVDD 0.6*AVDD MAX. 26.0 30.0 52.0 74.0 150 10 100 10 10 10 -25 VDDIO+0.3 VDDIO*0.2 VDDIO+0.3 VDDIO*0.15 0.8 2.5 VDDIO 0.4 VDDIO 0.4 VDDIO 0.4 VDDIO 0.3 0.525*AVDD 0.53*AVDD Unit
Technical Note
Condition
MHz XIN1 (Duty 5010%), at PLL ON MHz XIN2 (Duty 5010%), at PLL ON MHz At PLL ON MHz At PLL ON mA mA A A A A A A A V V V V V V V V V V V V V V V V V V V At Preview operating At AAC decode operating at 44kfs, Auto Play from Flash At suspend mode setting VIH=VDDIO1,2,3,4 Pull-down terminal, VIH=VDDIO2 Pull-up terminal, VIH=VDDIO2 VIL=GND Pull-down terminal, VIL=GND Pull-up terminal, VIL=GND Normal type input Normal type input Hysteresis input VDDIO1(CSB,WRB,RDB) VDDIO4(XIN1,XIN2) USB_DP,USB_DM Single-ended input voltage level ABS(VUSB_DP-VUSB_DM) Include VDI range IOH1=-1.0mA(DC), Normal type output (Including output mode of I/O terminal) IOL1=1.0mA(DC), Normal type output (Including output mode of I/O terminal) IOH1=-2.0mA(DC), CAMCKO IOL1=2.0mA(DC), CAMCKO IOH1=-4.0mA(DC), SD_CLK IOL1=4.0mA(DC), SD_CLK IOH1=-2.53mA(DC), USB_DP,USB_DM IOL1=2.53mA(DC), USB_DP,USB_DM IOUT=0A(no load),VREF IOUT=0A(no load). In Silence
VPP Theoretical Value of Dynamic range KOhm R_OUT,L_OUT,MONO_OUT
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Block Diagram
VIB0 LED0 SDC/MMC Interface SD Card/MMC I/F NAND Flash Interface NAND Flash I/F Audio sequencer for AutoPlay Out sync
Technical Note
FIFO 2KB
Audio Processor Audio path switch
DAC Audio Interface IIS I/F
FIFO 1KB
MIDI engine
FIFO 1KB
ADPCM Codec
PCM I/F
HOST Interface HOST I/F Register Array
LCD control display data LCD controller I/F
YUV=4:2:2 RGB=5:6:5 2-line serial control 2-line type serial for Camera, TVEncoder YUV=4:2:2 Brightness compenent D range change
RGB YUV color space conversion
TV Encoderr I/F TV Encoder Interface
1/n resizing cropping YUV=4:4:4 multistep zoom Camera Interface Max UXGA (1600x1200) Image processing (filter processing) YUV=4:2:2 JPEG Codec Memory I/F
LCD display frame memory 160KB Viewing Buffer memory 64KB Expanded overlay memory 32KB Mask memory 10KB Multi step zoom memory 4KB MIDI engine work memory Audio Processor work memory
Audio Processor Sequence Date/ MIDI Wave Data 192KB
Play List 16KB
CAMRST General purpose Input/output
Clock control Power down control
internal clock USB FS I/F Interrupt to HOST from each blocks Interrupt controller
PLL (2 channels) XIN1,XOUT1 XIN2,XOUT2 RESETB USB Interface
Recommended Application Circuit
Cam era
Ma i n LCD
CAMD[7:0] SDC
CAMCKI CAMVS,CAMHS
CAMCKO
SDA
TV -Encoder
TE_PIXCLK TE_VSYNC TE_HSYNC TED[7:0]
LCDCS1B LCDA0 LCDWRB LCDRDB LCDD[15:0] LCDD[16] Sub LCD
U SB H os t
USB_DP USB_DM
LCDD[17] LCDCS2B
B U6 5 6 9 GVW
AFE PCMDIN FSYNC DCLK DIGLR DIGCK INT DIGDOUT RDB D[15:0] DIGDIN CSB WRB A2 A1 FL_CEB FL_RB NAND Flash SD_CLK SD_CMD SD_DAT0 LCDD[3:1] SD C/MMC
H os t CPU
Data is prepared separately about each register setup. Please refer to the Development Scheme on page 14.
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Terminal functions
PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Land No. A1 C3 B2 B1 C2 D3 D2 D1 E3 E2 E1 E5 E4 F2 F1 F5 F4 F3 G1 G2 G3 G4 H1 H3 J1 J2 H4 H2 K1 G5 L1 L2 K3 H5 K2 J3 K4 L3 F6 G6 J4 L4 K5 H6 J5 L5 K6 F7 G7 L6 H7 K7 J6 L7 F8 GND D8 D7 D6 D5 D4 VDD D3 D2 D1 D0 ADVB CSB WRB RDB INT RESETB LED0 VIB0 DIGLR DIGCK DACMCK DIGDIN DIGDOUT FSYNC PCMDIN DCLK VDDIO1 L_OUT R_OUT AVSS AVDD AVSS VREF MONO_OUT VDDIO3 USB_DM USB_DP USB_RDY GND VDDIO2 SD_CLK SD_CMD VDD SD_DAT0 FL_CEB FL_RB LCDCS1B LCDCS2B LCDWRB / FL_WEB LCDRDB / FL_REB LCDA0 / FL_ALE TEST LCDD0 / FL_D0 LCDD1 / FL_D1 / SD_DAT1 PIN Name In/Out /Analog In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In In In In Out In Out Out In/Out In/Out In/Out In Out In/Out In In/Out Analog Analog Analog Analog Analog Analog In/Out Out In/Out In/Out Out In Out Out Out Out Out In In/Out In/Out Active Level GND DATA DATA DATA DATA DATA PWR DATA DATA DATA DATA Low Low Low Low * Low CLK CLK DATA DATA DATA CLK PWR DATA DATA GND PWR GND DATA PWR GND PWR CLK DATA PWR DATA Low Low Low Low Low Low * Low DATA DATA Init In *1 In *1 In *1 In *1 In *1 In *1 In *1 In *1 In *1 Low Low Low In In Out/Low In In In In Out/Low Out/Low Out/Low High Out/Low Out/Low Digital ground Host data bus: bit 8 Host data bus: bit 7 Host data bus: bit 6 Host data bus: bit 5 Host data bus: bit 4 CORE power supply Host data bus: bit 3 Host data bus: bit 2 Host data bus: bit 1 Host data bus: bit 0 Address latch enable Chip select signal Write enable signal Read enable signal Interrupt signal System reset signal LED control signal Vibrator control signal Sampling clock for audio data Bit clock for audio data (64Fs/32Fs) Master clock for audio data(256Fs/384Fs) Audio data input Audio data output Sampling clock for PCM data PCM data input Bit clock for PCM data Digital I/O power supply (System 1) Stereo L-channel analog output *12, *13 Stereo R-channel analog output *12, *13 Analog ground Analog power supply Analog ground AC (signal) GND Be sure to connect a 1-F bypass capacitor between VREF and AVSS. Monaural analog output *13, *14 USB power supply (System 3) UBS D- pin USB D+ pin I/O port for USB intialization Digital ground Digital I/O power supply (System 2) SD card clock output SD card command input/output Core power supply SD card data: bit0 NAND Flash chip enable NAND Flash Ready/Busy LCD controller chip select signal 1 LCD controller chip select signal 2 LCD controller write enable signal / NAND Flash write enable signal LCD controller read enable signal / NAND Flash read enable signal LCD controller command parameter identification signal/ NAND Flash address latch enable signal Test mode terminal (Connect to GND.) LCD controller data bus: bit 0 / NAND Flash data bus: bit 0 LCD controller data bus: bit 1 / NAND Flash data bus: bit 1 / SD card IF bus: bit 1 Function explanation
Technical Note
Power source system 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A A A A A A A 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Function division HOST HOST HOST HOST HOST HOST HOST HOST HOST HOST HOST HOST HOST HOST SYS SYS SYS AUD AUD AUD AUD AUD AUD AUD AUD AUD AUD AUD AUD USB USB USB SD SD SD FL FL LCD LCD LCD / FL LCD / FL LCD / FL SYS LCD / FL LCD / FL / SD
I/O type D*2 D*2 D*2 D*2 D*2 D*2 D*2 D*2 D*2 G G*3 G G C B D*4 D*4 D*5 D*5 D*5 D*6 D*7 D*5 D*6 D*5 I I J I H H D*3 C D*3 D*3 D*4 G*3 D*7 D*7 D*7 D*7 D*7 A D*3 D*3
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PIN No. 56 Land No. G8 PIN Name LCDD2 / FL_D2 / SD_DAT2 LCDD3 / FL_D3 / SD_DAT3 LCDD4 / FL_D4 LCDD5 / FL_D5 LCDD6 / FL_D6 LCDD7 / FL_D7 GND LCDD8 / FL_D8 LCDD9 / FL_D9 LCDD10 / FL_D10 LCDD11 / FL_D11 LCDD12 / FL_D12 LCDD13 / FL_D13 LCDD14 / FL_D14 LCDD15 / FL_D15 LCDD16 / SCL / FL_WPB LCDD17 / SI / FL_CLE VDDIO2 CAMRST SDA SDC CAMCKI CAMCKO CAMVS CAMHS VDD CAMD0 CAMD1 CAMD2 CAMD3 CAMD4 CAMD5 CAMD6 CAMD7 GND VDDIO2 TE_VSYNC TE_HSYNC TE_PIXCLK TED0 TED1 TED2 TED3 TED4 TED5 TED6 TED7 GND In/Out /Analog In/Out Active Level DATA Init Function explanation LCD controller data bus: bit 2 / NAND Flash data bus: bit 2 / SD card IF bus: bit 2 LCD controller data bus: bit 3 / NAND Flash data bus: bit 3 / SD card IF bus: bit 3 LCD controller data bus: bit 4 / NAND Flash data bus: bit 4 LCD controller data bus: bit 5 / NAND Flash data bus: bit 5 LCD controller data bus: bit 6 / NAND Flash data bus: bit 6 LCD controller data bus: bit 7 / NAND Flash data bus: bit 7 Digital ground LCD controller data bus: bit 8 / NAND Flash data bus: bit 8 LCD controller data bus: bit 9 / NAND Flash data bus: bit 9 LCD controller data bus: bit 10 / NAND Flash data bus: bit 10 LCD controller data bus: bit 11 / NAND Flash data bus: bit 11 LCD controller data bus: bit 12 / NAND Flash data bus: bit 12 LCD controller data bus: bit 13 / NAND Flash data bus: bit 13 LCD controller data bus: bit 14 / NAND Flash data bus: bit 14 LCD controller data bus: bit 15 / NAND Flash data bus: bit 15 LCD controller data bus: bit 16 / LCD serial transfer clock signal / NAND Flash write protect LCD controller data bus: bit 17 / LCD serial transfer clock signal / NAND Flash command enable Digital I/O power supply (System 2) Camera reset signal two-wire serial data two-wire serial clock Camera clock input Camera clock output Camera vertical timing signal Camera horizontal timing signal Core power supply Camera data input: bit 0 Camera data input: bit 1 Camera data input: bit 2 Camera data input: bit 3 Camera data input: bit 4 Camera data input: bit 5 Camera data input: bit 6 Camera data input: bit 7 Digital ground Digital I/O power supply (System 2) TV encoder interface Vertical sync TV encoder interface Horizontal sync TV encoder interface output clock TV encoder interface data: bit 0 TV encoder interface data: bit 1 TV encoder interface data: bit 2 TV encoder interface data: bit 3 TV encoder interface data: bit 4 TV encoder interface data: bit 5 TV encoder interface data: bit 6 TV encoder interface data: bit 7 Digital ground
Technical Note
Power source system 2 Function division LCD / FL / SD LCD / FL / SD LCD / FL LCD / FL LCD / FL LCD / FL LCD / FL LCD / FL LCD / FL LCD / FL LCD / FL LCD / FL LCD / FL LCD / FL LCD / FL LCD / FL CAM SYS SYS CAM CAM CAM CAM CAM CAM CAM CAM CAM CAM CAM CAM TV TV TV TV TV TV TV TV TV TV TV I/O type
Out/Low
D*3
57 58 59 60 61 62 63 64 65 66 67 68 69 70 71
L8 K8 J7 L9 L10 L11 H8 K9 K10 K11 J8 J9 J11 J10 H9
In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out
DATA DATA DATA DATA DATA GND DATA DATA DATA DATA DATA DATA DATA DATA DATA / DATA / Low DATA / CLK / High PWR DATA DATA CLK CLK CLK * * PWR DATA DATA DATA DATA DATA DATA DATA DATA GND PWR Low Low CLK DATA DATA DATA DATA DATA DATA DATA DATA GND
Out/Low Out/Low Out/Low Out/Low Out/Low Out/Low Out/Low Out/Low Out/Low Out/Low Out/Low Out/Low Out/Low Out/Low
2 2 2 2 2 2 2 2 2 2 2 2 2 2
D*3 D*3 D*3 D*3 D*3 D*3 D*3 D*3 D*3 D*3 D*3 D*3 D*3 D*3
72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103
H10 H11 G11 F11 G10 F10 E11 G9 F9 D11 E10 C11 D10 C10 B11 E9 E8 B10 A11 A10 D9 C9 B9 A9 D8 C8 A8 B8 A7 E7 D7 C7
In/Out In/Out In/Out In/Out In*9 Out In*9 In*9 In*9 In*9 In*9 In*9 In*9 In*9 In*9 In*9 Out Out Out Out Out Out Out Out Out Out Out -
Out/Low Out/Low Out/Low Out/Low Low High High Low High Low Low Low Low Low Low Low -
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 -
D*3 D*3 F F A C A A A A A A A A A A D*7 D*7 D*7 D*7 D*7 D*7 D*7 D*7 D*7 D*7 D*7 -
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Technical Note
PIN No. 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
Land No. A6 B7 B6 A5 C6 D6 E6 A4 B5 B3 C5 D5 A3 B4 C4 D4 A2
PIN Name VDDIO4 XIN1 XOUT1 PLL_FILTER XIN2 XOUT2 VSS4 VDDIO1 A2 A1 D15 D14 D13 D12 D11 D10 D9
In/Out /Analog In Out Analog In Out In In In/Out In/Out In/Out In/Out In/Out In/Out In/Out
Active Level PWR CLK CLK CLK CLK GND PWR DATA DATA DATA DATA DATA DATA DATA DATA DATA
Init In High In High In In In *1 In *1 In *1 In *1 In *1 In *1 In *1
Function explanation PLL power supply (System 4) Oscilator input1 *10 Oscilator output1 Be sure to connect a 2200-F bypass capacitor between PLL_FILTER and VSS4. Oscilator input2 *10 Oscilator output2 PLL ground Digital I/O power supply (System 1) Host address bus: bit 2 Host address bus: bit 1 Host data bus: bit 15 Host data bus: bit 14 Host data bus: bit 13 Host data bus: bit 12 Host data bus: bit 11 Host data bus: bit 10 Host data bus: bit 9
Power source system 4 4 4 4 4 4 4 1 1 1 1 1 1 1 1 1 1
Function division CLK CLK CLK CLK CLK HOST HOST HOST HOST HOST HOST HOST HOST HOST
I/O type E,G*11 E K E,G *11 E D*8 D*8 D*2 D*2 D*2 D*2 D*2 D*2 D*2
In the function division column, "HOST" stands for HOST IF, "SYS"SYSTEM, "CAM"CAMERA IF, "LCD"LCD IF, "AUD"Audio IF, "SD"SD Card IF, "FL"NAND Flash IF, "TV"TV Encoder IF, "USB"USB IF, and "CLK"OSC&PLL. In the power source system column, "1" stands for system 1 (VDDIO1), "2" for system 2 (VDDIO2), "3" for system 3 (VDDIO3), "4" for system 4 (VDDIO4), "A" for system 5 (ADD). "" in Active level column means active level can be changed by setting of register. Init column is a pin state at the time of reset release. *1 : RESETB="L" *2 : Pull-down only a test mode. *3 : Suspend only a test mode. *4 : Suspend or input only a test mode. *5 : Suspend or Pull-down only a test mode. *6 : Suspend, Pull-down or output function only a test mode. *7 : Suspend, Pull-down or input function only a test mode. *8 : Output or pull-down only a test mode. *9 : Pull-down during CAMOFF mode. *10 : The crystal oscillation circuit does not include a return resistance, so it is needed to examine an external circuit including return resistance. *11 : I/O type is E at oscillation mode, it is G at external clock input mode. *12 : When not during playback, the potential approximates Vref. Hi-Z at reset. *13 : When disable reset, standby, anout_disable or mono_disable, pop noise occurs. *14 : This pin outputs inverted signal of (R + L) / 2, If "monaural mode" is not selected. And outputs differential signal with L_OUT, If "monaural mode" is selected.
Equivalent Circuit Structures of input / output pins
Type
VDDIO
Equivalent circuit structure
VDDIO Internal signal
Type
Equivalent circuit structure
VDDIO
A
To internal
B
To internal
GND
GND
GND
GND
PULL-DOWN input terminal
Hysteresis input terminal
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BU6569GVW
Type
VDDIO
Technical Note
Equivalent circuit structure
VDDIO Internal signal
Type
Equivalent circuit structure
VDDIO To internal VDDIO
VDDIO
Internal signal
C
Internal signal
D
Internal signal GND Internal signal
GND
GND
GND
GND
Internal signal
Output terminal
VDDIO VDDIO VDDIO XIN VDDIO
Suspend, PULL-DOWN I/O terminal
VDDIO Internal signal VDDIO VDDIO
VDDIO GND To
Internal signal
E
VDDIO
Internal
F
signal
internal GND Internal signal
XOUT
GND
To internal
GND
Internal signal GND GND GND
Clock input terminal
VDDIO
PULL-UP I/O terminal
Internal signal
Internal signal VDDIO
VDDIO To internal
G
H
Internal signal
GND
Internal signal
GND
GND
Internal signal
Suspend, hysteresis input terminal
AVDD
USB
AVDD AVDD
Internal signal
I
J
Internal signal
AVSS AVSS AVSS
AVSS
DAC_OUT
VDDIO4 Internal signal
VREF
K
Internal signal
VSS4
PLL_FILTER
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9/16
2009.07 - Rev.A
BU6569GVW
Terminal Layout
Technical Note
31 AVSS
32 AVDD
38 USB_DP
42 SD_CLK
46 FL_CEB
50 LCDWRB
54 LCDD0
57 LCDD3
60 LCDD6
61 LCDD7
62 GND
29 L_OUT
35 MONO_OUT
33 AVSS
37 USB_DM
43 SD_CMD
47 FL_RB
52 LCDA0
58 LCDD4
64 LCDD9
65 LCDD10
66 LCDD11
25 FSYNC
26 PCMDIN
36 VDDIO3
41
45 SD_DAT0
53 TEST
59 LCDD5
67 LCDD12
68 LCDD13
70 LCDD15
69 LCDD14
23 DIGDIN
28 VDDIO1
24 DIGDOUT
27
34 VREF
44 VDD
51 LCDRDB
63 LCDD8
71 LCDD16
72 LCDD17
73 VDDIO2
19 VIB0
20 DIGLR
21 DIGCK
22
30 R_OUT
40 GND
49 LCDCS2B
56 LCDD2
79 CAMVS
76 SDC
74 CAMRST
15 RDB
14 WRB
18 LED0
17
16 INT
39 USB_RDY
48 LCDCS1B
55 LCDD1
80 CAMHS
77 CAMCKI
75 SDA
11 D0
10 D1
9 D2
13
12 ADVB
110 VSS4
101 TED6
88 CAMD6
87 CAMD5
82 CAMD0
78 CAMCKO
8 D3
7 VDD
6 D4
119
115 D14
109 XOUT2
102 TED7
96 TE_D1
92 TE_VSYNC
84 CAMD2
81 VDD
5 D5
2 D8
118
114 D15
108 XIN2
103 GND
97 TED2
93 TE_HSYNC
85 CAMD3
83 CAMD1
4 D6
3 D7
113 A1
117
112 A2
106 XOUT1
105 XIN1
99 TED4
94 TE_PIXCLK
89 CAMD7
86 CAMD4
1 GND
120 D9
116 D13
111
107 PLL_FILTER
104 VDDIO4
100 TED5
98 TED3
95 TED0
91 VDDIO2
90 GND
1
2
3
4
5
6
7
8
9
10
11
Bottom View
Timing Chart 1. HOST interface timing 1.1 System timing Table 1.1
Symbol tXIN tXIN2 DutyXIN tSCLK DutySCLK tCAMCKO DutyCAMCKO tCAMCKI DutyCAMCKI tRESETB Details BU6569GVW Clock input cycle BU6569GVW Clock input cycle 2 BU6569GVW clock duty BU6569GVW SCLK clock cycle BU6569GVW SCLK clock duty Camera clock output cycle Camera clock output duty Camera clock input cycle Camera clock input duty RESETB "L" pulse width
BU6569GVW timing conditions (system)
MIN. 38.5 33.3 45.0 19.2 33.3 19.2 33.3 19.2 45.0 1.0 TYP. 50.0 50.0 50.0 50.0 MAX. 372.0 100.0 55.0 66.6 66.6 55.0 Unit ns ns % ns % ns % ns % s "H" width / cycle "H" width / cycle "H" width / cycle "H" width / cycle Conditions
Regulation all at threshold of VDDIO1/2
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10/16
2009.07 - Rev.A
BU6569GVW
1.2 Register (including RAM via register) write timing.
tWC tAS tAH Address Input
Technical Note
A2,A1 CSBWRB WRBCSB RDB
tDS tDH Data Write tCS tWW tWAIT tCH
D[15:0] Table 1.2
Symbol tWC tAS tAH tCS tCH tWW tWAIT tDS tDH Write cycle time Address setup time before WRB(CSB) falling Address hold time after WRB(CSB) rising CSB(WRB) input setup time before WRB(CSB) falling CSB(WRB) input hold time after WRB(CSB) falling WRB(CSB) active time width Wait time from WRB(CSB) rising to the next WRB(CSB) or to RDB falling Data setup time before WRB(CSB) rising Data hold time after WRB(CSB) rising
BU6569GVW timing conditionsRAM, register write cycle
Details MIN. 80 -7 -1 0 0 45 5.5 40 -1 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns
Regulation all at threshold of VDDIO1/2VDD=1.50V,VDDIO=3.30V,GND=0V,Ta=25 It is possible to use it with either CSB or WRB active. However, either of them must do LOW pulse operation.
1.3 Register (including RAM via register) read timing.
tAS tRC tAH Address Input
A2,A1 CSBRDB WRB RDBCSB
tROE tCS tRD
tCH
tWAIT tROD Read Data
D[15:0] Table 1.3-1
Symbol tRC tAS tAH tCS tCH tRD tWAIT tROE,tROD Read cycle time Address setup time before RDB(CSB) falling Address hold time after RDB(CSB) rising CSB(RDB) input setup time before RDB(CSB) falling CSB(RDB) input hold time after RDB(CSB) rising Access time after RDB(CSB) falling
BU6569GVW timing conditions (RAM, register read cycle)
Details MIN. 110 -7 -1 0 0 5.5 TYP. MAX. 70 15 Unit ns ns ns ns ns ns ns ns
Wait time from RDB(CSB) falling to the next RDB(CSB) falling or to WRB falling
Data output enable time after RDB(CSB) rising, Data output disable time after RDB(CSB) falling
Regulation all at threshold of VDDIO1/2VDD=1.50V,VDDIO=3.30V,GND=0V,Ta=25 It is possible to use it with either CSB or WRB active. However, either of them must do LOW pulse operation.
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11/16
2009.07 - Rev.A
BU6569GVW
2. Camera Module Interface Timing 2.1. System clock and camera clock
Technical Note
BU6569GVW external clock input (XIN) can be divided and supplied as CAMCKO clock to camera module. The relation between data synchronization CAMCKI clock from camera and system clock SCLK must be set in order to meet the following formula by setting of ACTSW (IDX:00D3h CLKDIV3[5:4]). When ACTSW=1h When ACTSW=2h Wherein, fSCLK fCAMCK1 fSCLK 2fCAMCKI Formula:2.1-1 Formula:2.1-2
fSCLK BU6569GVW system clock frequency fCAMCKI CAMCKI terminal input clock frequency ACTSW=0h,3h is forbidden. (note) fCAMCKI fSCLK, 2fCAMCKI fSCLK fCAMCKI is forbidden. 2.2. Camera module interface image data timing The timing of the camera image signal in camera I/F is shown in Figure 2.2-1.
CAMVS CAMHS CAMD0CAMD7 CAMCKI (CKPOL='0') CAMCKI (CKPOL='1') tCMS tCMH Symbol tCMS tCMH Details camera data setup time camera data hold time MIN. 4 4 TYP. MAX. Unit ns ns
Regulation all at threshold of VDDIO21/2
Figure 2.2-1 BU6569GVW timing (camera image data) 3. LCD direct access
Transparent terminal timing at LCD module direct access CSB LCDCSB WRB LCDWRB RDB LCDRDB A1 LCDA0 D0D15 LCDD0LCDD17
tDTw1 tAD1 tCSf1 tWRr1 tWRf1 tRDr1 tRDf1 tAD1 tDTr1
tCSr1
Figure 3-1
BU6569GVW timing conditions (LCD direct access
Table 3-1
Symbol tCSf1 tCSr1 tWRf1 tWRr1 tRDf1 tRDr1 tAD1 tDTw1
BU6569GVW timing conditionsLCD direct access
Details MIN. 4.3 2.6 4.9 2.6 5.1 2.9 3.6 4.5 4.1 TYP. MAX. 16.0 10.5 17.1 11.4 17.2 11.6 13.3 14.4 13.1 Unit ns ns ns ns ns ns ns ns ns
Delay from CSB to LCDCSB falling Delay from CSB to LCDCSB rising Delay from WRB to LCDWRB falling Delay from WRB to LCDWRB rising Delay from RDB to LCDRDB falling Delay from RDB to LCDRDB rising Delay from A1 to LCDA0 Delay from D0D15 to LCDD0LCDD17
tDTr1 Delay from LCDD0LCDD17 to D0D15 Regulation all at threshold of VDDIO1/2
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12/16
2009.07 - Rev.A
BU6569GVW
4. LCD transfer timing Transfer timing to LCD is shown below.
LCDCSB1 LCDA0 2 LCDWRB WL+1 LCDD0-17 COMMAND transfer DATA transfer WL+1 WL+1 WL+1 WL+1
Technical Note
WH+1
WH+1
WH+1
WH+1
WH+2
Without COMMAND transfer, this portion will be skipped.
(WH and WL can be set from 0 to 15.)
Figure 4-1 5. Digital input interface timing 5.1. IIS input timing The input timing in IIS I/F is shown below.
DIGLR DIGDIN DIGCK tIISS tIISH
MAIN LCD data transfer waveformUnittSCLK
Symbol
tIISS tIISH
Details
IIS input data setup time IIS input data hold time
MIN.
5 5
TYP.
-
MAX.
-
Unit
ns ns
Regulation all at threshold of VDDIO11/2
5.2. PCM input timing The input timing in PCM I/F is shown below.
FSYNC
Symbol
PCMDIN DCLK (DCLK Polarity='0') DCLK (DCLK Polarity='1') tPCMS tPCMH
Details PCM data setup time PCM data hold time
MIN.
5 5
TYP.
-
MAX.
-
Unit
ns ns
tPCMS tPCMH
Regulation all at threshold of VDDIO11/2
6.
SD Card I/F / MMC I/F input / output timing
tTRlh tTRhl
(Host to/from SD Card)
SD Card I/F / MMC I/F input
SD Card I/F / MMC I/F output
SDCLK tODcmd SDCMD tODdat SDDAT0-3
SDCLK
tSUcmd
tHDcmd
SDCMD tSUdat SDDAT0-3 tHDdat
Table 1.6-1 BU6569GVW timing conditionsSD Card I/F / MMC I/F output
Symbol tTRlh tTRhl tODcmd tODdat Details SDCLK clock rise time SDCLK clock fall time SDCMD output delay against SDCLK falling SDDAT0-3 output delay against SDCLK falling MIN. -2 () -2 () TYP. MAX. 5() 5() 2 () 7 ()
Unit
Table 1.6-2 BU6569GVW timing conditionsSD Card I/F / MMC I/F input
Symbol tSUcmd tHDcmd tSUdat tHDdat Details SDCMD setup time SDCMD hold time SDDAT0-3 setup time SDDAT0-3 hold time MIN. 7 1 10 1 TYP. MAX. Unit
ns ns ns ns
ns ns ns ns
()At no load condition Regulation all at threshold of VDDIO21/2
Regulation all at threshold of VDDIO21/2
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13/16
2009.07 - Rev.A
BU6569GVW
Technical Note
Development Scheme This technical note is aimed at trying the connectivity in the hardware between customer's system and our camera image processor series. We prepare various data and tools for every development STEP as follows other than this technical note, please contact the sales staff in your duty also including the support system. 1 Demonstration STEP (You can try the standard image processing functions by the standard Demonstration kit at once.) You can confirm the standard functions such as camera image preview, memory data display to LCD, camera image composition JPEG compression/ expansion, frame composition, divided display, and LED lighting, and so forth on the Demonstration board. Standard Demonstration board kit Demonstration board LCD module provided by ROHM, Camera module provided by ROHM, Check board equipped with the camera image processor, ARM-equipped controller board Demonstration board operation manual Demonstration software If the software for the trial board is installed in your Windows PC(Windows 2000/XP/ME/98), more detailed setting is possible. (Execution tools for the macro command, sample macro command file) USB cable 2 Confirmation STEP (We will respond to customer's camera module, LCD module, HOST CPU.) Specifications We will provide specifications for camera image processor according to customer's requirements. Function explanation We will deliver you the function explanation describing detailed functions, register settings, external interfaces, timing, and so forth of camera image processor according to your requests. Application note
We will deliver you the detailed explanation data on application development of camera image processor according to your requests.
3
System check STEP (You can check the application operation as a system by the kit of system check tools and your module(camera/LCD).) ROHM creates the system check board using your camera/LCD module. You can check the interface with your module and the application operation on the system check board using the tools for user's only. System check tools kit System check software (For Windows PC) Reference C source code summarizing ARM -compatible application program interface(API) The application software (API) as a reference C source code The execution tools for the macro command (BU65XX_USB) for the check by your PC. The macro command file for the check by your PC. System check document System check board manual BU65XX Demo_Board Application using API Board circuit diagram
*You can check the detailed functions of the application operation by your PC using the macro command file.
4
Integrated check STEP with user's system (You can check the application operation as a system on your system check board using the integrated check software.) You can check the application operation on the sample LSI-equipped system check board by your camera / LCD module using the integrated check software. On line SupportWe will answer your questions about the software development. How to use the macro command file, API file, and APL file. Setting flow of the camera function (camera JPEG, preview, etc.) Interface setting of the camera module, LCD module and the camera image processor. Header analysis method oh JPEG decode, etc. On site SupportWe will help you clarify the questions about the software development on site together on spot. Check of the operation of each function and the basic operation at each register setting, etc. based on the specification. Explanation about the specific usage of the macro command file, API file and APL file and relative questions. How to develop the overlay or special functions, etc.
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14/16
2009.07 - Rev.A
BU6569GVW
Cautions on use (1)Absolute Maximum Ratings
Technical Note
An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down devices, thus making impossible to identify breaking mode such as a short circuit or an open circuit. If any special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical safety measures including the use of fuses, etc.
(2)Operating conditions
These conditions represent a range within which characteristics can be provided approximately as expected. The electrical characteristics are guaranteed under the conditions of each parameter.
(3)Reverse connection of power supply connector
The reverse connection of power supply connector can break down ICs. Take protective measures against the breakdown due to the reverse connection, such as mounting an external diode between the power supply and the IC's power supply terminal.
(4)Power supply line
Design PCB pattern to provide low impedance for the wiring between the power supply and the GND lines. In this regard, for the digital block power supply and the analog block power supply, even though these power supplies has the same level of potential, separate the power supply pattern for the digital block from that for the analog block, thus suppressing the diffraction of digital noises to the analog block power supply resulting from impedance common to the wiring patterns. For the GND line, give consideration to design the patterns in a similar manner. Furthermore, for all power supply terminals to ICs, mount a capacitor between the power supply and the GND terminal. At the same time, in order to use an electrolytic capacitor, thoroughly check to be sure the characteristics of the capacitor to be used present no problem including the occurrence of capacity dropout at a low temperature, thus determining the constant.
(5)GND voltage
Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state. Furthermore, check to be sure no terminals are at a potential lower than the GND voltage including an actual electric transient.
(6)Short circuit between terminals and erroneous mounting
In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting can break down the ICs. Furthermore, if a short circuit occurs due to foreign matters entering between terminals or between the terminal and the power supply or the GND terminal, the ICs can break down.
(7)Operation in strong electromagnetic field
Be noted that using ICs in the strong electromagnetic field can malfunction them.
(8)Inspection with set PCB
On the inspection with the set PCB, if a capacitor is connected to a low-impedance IC terminal, the IC can suffer stress. Therefore, be sure to discharge from the set PCB by each process. Furthermore, in order to mount or dismount the set PCB to/from the jig for the inspection process, be sure to turn OFF the power supply and then mount the set PCB to the jig. After the completion of the inspection, be sure to turn OFF the power supply and then dismount it from the jig. In addition, for protection against static electricity, establish a ground for the assembly process and pay thorough attention to the transportation and the storage of the set PCB.
(9)Input terminals
In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the parasitic element can cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the input terminal. Therefore, pay thorough attention not to handle the input terminals, such as to apply to the input terminals a voltage lower than the GND respectively, so that any parasitic element will operate. Furthermore, do not apply a voltage to the input terminals when no power supply voltage is applied to the IC. In addition, even if the power supply voltage is applied, apply to the input terminals a voltage lower than the power supply voltage or within the guaranteed value of electrical characteristics.
(10)Ground wiring pattern
If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well.
(11)External capacitor
In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation in the nominal capacitance due to DC bias and changes in the capacitance due to temperature, etc.
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15/16
2009.07 - Rev.A
BU6569GVW
Order Model Name Selection
Technical Note
B
U
6
5
6
9
GVW
Package type GVW: SBGA120W080
E
2
ROHM model name
Product number
Taping model name E2: Embossed reel tape
SBGA120W080
1PIN MARK 8.00.1

Tape
8.00.1
Embossed carrier tape (with dry pack) 1000pcs E2
The direction is the 1pin of product is at the upper left when you hold
Quantity Direction of feed
0.08 0.9MAX
S
( reel on the left hand and you pull out the tape on the right hand
)
0.1
S P=0.65x10 0.750.1 0.65 A
L K J H G F E D C B A
120- 0.330.05 0.05 M S AB
B
0.65 0.750.1 P=0.65x10
1 3 5 7 9 11 2 4 6 8 10
1pin
Direction of feed
(Unit : mm)
Reel
Order quantity needs to be multiple of the minimum quantity.
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16/16
2009.07 - Rev.A
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact us.
ROHM Customer Support System
http://www.rohm.com/contact/
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